VSD - Custom Layout Udemy CourseDownload Course
VSD - Custom Layout Course Created by Kunal Ghosh.
VSD - Custom Layout has 4.3 rating out of 5 based on 251 students. Currently this course has 1,495 students. Course langwage is English.
VSD - Custom Layout Course Description
Physical designers and CMOS fabrication teams communicate with each other and say 'how?' during this process.
Physical designers use all the output of experiments performed by the fabrication department, but this process shows the best of both worlds and links them by exchanging specific files in specific formats.
This gives custom layout designers insight into how fabrication works, and how fabrication engineers use their information. So this process is a place where two people meet, talk and connect.
Also, the standard files needed to draw and simulate layouts are imported, inferred, and generated on the fly from scratch. This is the best way to understand the layout and promises an exciting journey through this course.
The course initially consists of the software and files used to describe the CMOS packaging and fabrication steps, draw and simulate the layout, and explore the DRC rules.
Next, take a simple CMOS inverter and apply all of the concepts learned above. Finally, you will learn the 'art of layout' using Euler's path. Here we solve complex functions and draw the layout.
Welcome to my courses and happy learning!!
See you in class!
Kunal Ghosh is a Director and Co-Founder of VLSI System Design (VSD) Corp. Pvt. Ltd. Prior to the VSD launch in 2017, Kunal was He has held several technical leadership positions in Qualcomm's Test Chip division. He joined Qualcomm in 2010. He led the physical design and STA flow development of the 28nm and 16nm test chips. In 2013 he joined Cadence as Lead Sales Applications Engineer for Tempus STA Tools. Kunal holds a master's degree in Electrical Engineering from India. IIT (Institute of Technology), Bombay, India, specializing in VLSI design and nanotechnology.
Using technology @
1) MSM (Mobile Station Mode Chip) - The MSM chip is used for CDMA modulation/demodulation. It consists of a DSP and a microprocessor to run applications such as web browsing, video conferencing, multimedia services, etc.
2) Memory Test Chip - The memory test chip is used to validate the functionality of 28nm custom/compiler memories and to characterize timing, power and yield.
3) DDR-PHY Test Chip - The DDR-PHY test chip is basically tested for high-speed data transfer.
4) Timing and Physical Design Flow development from 130nm MOSFET technology node to 16nm FinFET technology node.
5) 'IR-aware STA' and 'Low-power STA'
6) Analysis of STA engine behavior for design sizes of up to 850 million instances academic
1) For the RAITH-150TWO electron beam lithography tool and "Sub-100nm optimization using electron beam lithography" to optimize process conditions to achieve minimum resolution, Professor Richard Pinto and Professor Anil Kottantharayil's research assistants use . The tool's mix-and-match capability for sub-100nm MOSFET fabrication and mask plate creation for feature sizes greater than 500nm.
2) Research assistant with Professor Madhav Desai to characterize RTL generated by C-to-RTL AHIR compiler in terms of power, performance and area. This was done by passing the RTL generated by the AHIR compiler through a standard ASIC toolchain such as synthesis and place and path. The resulting netlist of PNRs was characterized using standard software.
1) “C-to- as an energy-efficient alternative to embedded processors in digital systems” presented at the “13th Euromicro Conference on Digital Systems Design, Architecture, Methods and Tools, DSD 2010, 1-3” conference RTL Flow” September 2010, Lille, France”
2) Concurrent + Distributed MMMC STAs for 'N' Views
3) Optimizing Signoff Timing and Leakage in 18M Instance Count Design with 8000 Clocks and Replicated Modules Using Master Clone Methodology with EDI Cockpit
4) Batch Aware ECO Methodology - No Slack in Slack
Tips on how to learn VLSI and become a champion:
If I were you, I would have started the Physical Design and Physical Design webinar course to understand the whole flow first, then moved on to CTS-1 and CTS-2 to take a closer look at how watches work. Built.
Then, now that you all know how crosstalk affects the functioning of the child nodes, let's understand and correct the effects of scaling through the signal integrity process. That way I would like to know how to analyze the performance of my design and have taken the STA-1, STA-2 and Timing ECO webinar courses respectively.
Being an STA creates an inner curiosity, hoping to understand what goes inside timing analysis at the transistor level. To complete this, I would have taken the Circuit Design and SPICE Simulation Part 1 and Part 2 courses.
Finally, if you want to better understand the pre-placed cells, IPs, and STAs, you may have taken the Custom Layout course and the Library Characterization course.
All of the above needs to be implemented using a CAD tool and should be done faster, so I would have written a TCL or perl script. To this end, I started learning TCL-Part1 and TCL-Part2 courses at the beginning or in the middle.
Finally, if you want to learn RTL and synthesis from specification to layout, the RISC-V ISA course will teach you the best way to define specifications for complex systems such as microprocessors.
Connect with me for more information!!
We hope you enjoy the best sessions for the future.
VSD - Custom Layout Course for
- Anyone curious to know the inception of layout
- Anyone curious to know the software behind layout drawing
- Anyone who wants to know how chip designers talk with chip fabrication department
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