FPGA Design with High Level Synthesis Tool (VIVADO HLS)

FPGA Design with High Level Synthesis Tool (VIVADO HLS) Udemy Course

FPGA Design with High Level Synthesis Tool (VIVADO HLS) Course Created by Digitronix Nepal.

FPGA Design with High Level Synthesis Tool (VIVADO HLS) has 3.6 rating out of 5 based on 86 students. Currently this course has 527 students. Course langwage is English.

FPGA Design with High Level Synthesis Tool (VIVADO HLS) Course Description

Learn Basic HLS Design and C-Simulation for Designing Computer Vision Applications [Real-Time Sobel Edge Detection]

High-level synthesis is a new approach to FPGA design using the C/C++ language. In this course, you will create a new project in HLS, run C simulations in HLS, synthesize an HLS project that converts C/C++ sources to Verilog/VHDL and run system C, C/RTL co-simulations, export HLS designs to IP core format - VIVADO IP Integrator. Also included is a session on "Designing Sobel Edge IP in HLS, Exporting to VIVADO Tools and Implementing/Testing on Zybo FPGAs".

Completing this course will allow you to design, simulate, synthesize, and implement/export your HLS project. HLS includes a number of C/C++ libraries for very complex computer vision (OpenCV), video/image processing and mathematical calculations while implementing in HDL/RTL.

In this lab, you will practice designing, simulating, synthesizing, and implementing (export design) counters, matrix multipliers, frequency modulators, and numerically controlled oscillators (NCO Design) in C++. It also integrates HLS projects exported from VIVADO IP Integrator with the Zynq Processing System, and implements and synthesizes projects in VIVADO IPI.

Digitronix Nepal is an FPGA design company serving customers worldwide since 2013. Digitronix Nepal has partnered with LogicTronix [an FPGA design and machine learning company] to create an online learning course as part of the "Global FPGA Education Democracy" initiative. Tutorials on "FPGA, VHDL/Verilog, Computer Vision and Video Processing, High Level Synthesis (HLS), MATLAB/System Generator, Machine Learning Acceleratio, SDAccel, SDSoC, Pynq Development, and more"

Digitronix Nepal believes that "Ultra Low Cost & Free Course" on FPGA Design allows enthusiasts from all countries to learn and explore the field of FPGA design and seize global opportunities for FPGA design, ASIC/VLSI design and machinery. Accelerate learning.